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Groton, CT Website Wallach Search Group Location: Groton, CT Security Clearance: US Citizen/Clearable We are looking for a highly motivated power electronics engineer to join our Sensing and Communications Department.
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You will also work with the ASIC design team to establish the prototyping systems required for verification of custom ASICs∯*∯ Experience with high density interconnect PCB design, high power systems (> 1kW), and a working knowledge of thermal design techniques will be helpful for this role.
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In-depth technical expertise in one or more areas - DRAM memory array design, high-speed clocking and interface development, analog circuit design, digital/logic and custom circuit design, power delivery optimization, CMOS & semiconductor device physics, 2.5D and 3D packaging technologies.
$184,000 - $323,000 a yearFull-timeExpandApply NowActive JobUpdated 7 days ago - UpvoteDownvoteShare Job
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Work with the integrated circuit designers and chip leads to determine the chip floor plan; this includes strategies for power and ground distribution as well as working with packaging engineer to determine pad locations.
$160,000 - $220,000ExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Candidate must be able to work with self-motivation and deliver on commitments with challenging schedules, lead design teams through various phases of ASIC design process including RTL design, chip level verification, coverage analysis, synthesis and STA. Candidate must possess solid knowledge in SOC design techniques, analog IPs, high speed IO protocols, CPF/UPF power design flow and lint/CDC tools.
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Work closely with chip architecture, design verification, physical design, DFT, and power teams to achieve tapeout success on designs – generally bridging the RTL and place and route. Execute low power design and physical synthesis, deploying knowledge of unified power format and power intent verification.
$170,000 - $230,000Full-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Knowledge of low power design emulation/verification and power management fundamentals Knowledge of UEFI, Core boot, Chrome, Windows Operating Systems Knowledge of x86 and/or ARM SoC Architecture Knowledge of Platform security, Secure protocols, Cryptographic applications Knowledge of one or more protocols; SPI, DDR, SATA, USB, AXI, PCI, PCIe, MIPI, WLAN or I2C The ideal candidate will be considered for a hybrid role with 1-2 days working from home.
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As a Senior Digital Design Engineer you will develop world class, highly integrated, low power, System on a Chip devices to serve the IoT wireless market. The IoT Digital Design team is a state-of-the-art IC design team focused on producing world class Wireless MCU SoCs. The architecture specification, design, verification, emulation, and implementation of the Wireless MCU SoCs are all the responsibilities of the IoT Digital team.
$114,428 - $212,510 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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In-depth knowledge and experience working with low-power design, UPF integration, boot-up, power cycling, and HW/FW interaction verification. As a Design Verification Engineer on our team, you'll be at the center of the verification effort within our silicon design group responsible for crafting and productizing innovative Cellular SoCs.
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The applicant should be familiar with computer system architecture, digital design, signal integrity and power integrity (SIPI), and design verification tests. To name a few of our core deliverables: - Signal integrity and power integrity (SIPI) simulation and validation - Power management system designs and validation - Clock management design and validations - Wireless system integration, schematic, PCB layout, BOM, and constraints, for both development platforms and for consumer products - High-speed and low-speed digital interfaces designs and validations - Failure analysis for wireless systems on our prototypes Everything is going wireless.
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Skills Desired - Experience in at least few of these: CPU (preferably, ARM), or GPU, or DSP; low-power design and verification; peripheral interfaces such as CSI, I3C, USB, PCIe; FPGA; image/video processing.
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Work in a team that drives architecture, design, implementation, and verification of RF/mixed-signal systems that include circuit blocks such as LNAs, Mixers, PAs, PLLs, VCOs, ADCs, DACs. Since then, we’ve developed a full line of products that drive 4G and 5G infrastructure; enable data center, metro and long-haul optical interconnects; bring 10Gbit to the home; power the IoT revolution; and enable robust and reliable communication in harsh industrial environments.
$110,100 - $170,890 a yearFull-timeExpandApply NowActive JobUpdated Today - UpvoteDownvoteShare Job
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Excellent experience with ASIC verification tools, simulation, linting, power aware simulation, etc. Hardware/Firmware co-verification in UVM System Verilog and C-DPI structured testbench.
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Solid knowledge on Low Power Design, DFT, static timing analysis and closure, data skew balancing, duty cycle adjustment, EM/IR-Drop/crosstalk analysis, formal verification, physical verification, DFM and P&R.
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As an ASIC Design Engineer in the Pixel IP design team, you will work closely with many multi-functional teams (chip integration, physical design, power, logic design, and verification) to build commitment and low power pixel processing engines.
$170,700 - $300,200 a yearExpandApply NowActive JobUpdated 8 days ago
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